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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">EDRCR, External Debug Reserve Control Register</h1><p>The EDRCR characteristics are:</p><h2>Purpose</h2>
        <p>This register is used to allow imprecise entry to Debug state and clear sticky bits in <a href="ext-edscr.html">EDSCR</a>.</p>
      <h2>Configuration</h2><p>EDRCR is in the Core power domain.
    </p><h2>Attributes</h2>
        <p>EDRCR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="27"><a href="#fieldset_0-31_5">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-4_4">CBRRQ</a></td><td class="lr" colspan="1"><a href="#fieldset_0-3_3">CSPA</a></td><td class="lr" colspan="1"><a href="#fieldset_0-2_2">CSE</a></td><td class="lr" colspan="2"><a href="#fieldset_0-1_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_0-31_5">Bits [31:5]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-4_4">CBRRQ, bit [4]</h4><div class="field">
      <p>Allow imprecise entry to Debug state. The actions on writing to this bit are:</p>
    <table class="valuetable"><tr><th>CBRRQ</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No action.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Allow imprecise entry to Debug state, for example by canceling pending bus accesses.</p>
        </td></tr></table><p>Setting this bit to 1 allows a debugger to request imprecise entry to Debug state. An External Debug Request debug event must be pending before the debugger sets this bit to 1.</p>
<p>This feature is optional. If this feature is not implemented, writes to this bit are ignored.</p></div><h4 id="fieldset_0-3_3">CSPA, bit [3]</h4><div class="field">
      <p>Clear Sticky Pipeline Advance. This bit is used to clear the <a href="ext-edscr.html">EDSCR</a>.PipeAdv bit to 0. The actions on writing to this bit are:</p>
    <table class="valuetable"><tr><th>CSPA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No action.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Clear the <a href="ext-edscr.html">EDSCR</a>.PipeAdv bit to 0.</p>
        </td></tr></table></div><h4 id="fieldset_0-2_2">CSE, bit [2]</h4><div class="field">
      <p>Clear Sticky Error. Used to clear the <a href="ext-edscr.html">EDSCR</a> cumulative error bits to 0. The actions on writing to this bit are:</p>
    <table class="valuetable"><tr><th>CSE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No action.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Clear the <a href="ext-edscr.html">EDSCR</a>.{TXU, RXO, ERR} bits, and, if the PE is in Debug state, the <a href="ext-edscr.html">EDSCR</a>.ITO bit, to 0.</p>
        </td></tr></table></div><h4 id="fieldset_0-1_0">Bits [1:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h2>Accessing EDRCR</h2><h4>EDRCR can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>Debug</td><td><span class="hexnumber">0x090</span></td><td>EDRCR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and SoftwareLockStatus(), accesses to this register are <span class="access_level">WI</span>.
          </li><li>When IsCorePowered(), !DoubleLockStatus(), !OSLockStatus() and !SoftwareLockStatus(), accesses to this register are <span class="access_level">WO</span>.
          </li><li>Otherwise, accesses to this register generate an error response.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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